A typical flash memory device includes a memory array having a large number of memory cells arranged in blocks. Each of the memory cells includes a field effect transistor having a control gate and a floating gate. The floating gate holds a charge and is separated from source and drain regions in a substrate by an oxide. Each memory cell can be electrically charged by electrons injected onto the floating gate. The charge may be removed from the floating gate by tunneling to the source region or an erase gate during an erase operation. The data in flash memory cells are thus determined by the presence or absence of charge in the floating gates.
It is a trend in memory devices to scale down the device size for packing density and cost. In a conventional flash memory structure, it is a challenge to shrink the word line length due to conflicting factors. For a split gate flash memory device, shorter length of the word line results in higher channel leakage and increased bit errors. If the channel dose is increased to reduce channel leakage, it will decrease read current of the erase operation and impact the endurance window after the operation cycling. Further, the leakage may cause a reading error. There is therefore a need for a flash memory structure with a reduced leakage current and a shortened word line length.